|I/O bus clock|
|Peak transfer rate|
Note: All above listed are specified by JEDEC as JESD79-3D. All RAM data rates in-between or above these listed specifications are not standardized by JEDEC—often they are simply manufacturer optimizations using higher-tolerance or overvolted chips. Of these non-standard specifications, the highest purported speed reached was equivalent to DDR3-2544 as of May 2010.
DDR3-xxx denotes data transfer rate, and describes raw DDR chips, whereas PC3-xxxx denotes theoretical bandwidth (with the last two digits truncated), and is used to describe assembled DIMMs. Bandwidth is calculated by taking transfers per second and multiplying by eight. This is because DDR3 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer.
In addition to bandwidth and capacity variants, modules can
- Optionally implement ECC, which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC or E in their designation. For example: "PC3-6400 ECC", or PC3-8500E. 
- Be "registered", which improves signal integrity (and hence potentially clock rates and physical slot capacity) by electrically buffering the signals with a register, at a cost of an extra clock of increased latency. Those modules are identified by an additional R in their designation, whereas non-registered (a.k.a. "unbuffered") RAM may be identified by an additional U in the designation. PC3-6400R is a registered PC3-6400 module, PC3-6400R ECC is the same module but with additional ECC.
- Be fully buffered modules, which are designated by F or FB and do not have the same notch position as other classes. Fully buffered modules cannot be used with motherboards that are made for registered modules, and the different notch position physically prevents their insertion.