Memory timing

There are many numbers required to describe the timing of DRAM operation. Here are some examples for two timing grades of asynchronous DRAM, from a data sheet published in 1998:^[3]

	"50 ns"	"60 ns"	Description
tRC	84 ns	104 ns	Random read or write cycle time (from one full /RAS cycle to another)
tRAC	50 ns	60 ns	Access time: /RAS low to valid data out
tRCD	11 ns	14 ns	/RAS low to /CAS low time
tRAS	50 ns	60 ns	/RAS pulse width (minimum /RAS low time)
tRP	30 ns	40 ns	/RAS precharge time (minimum /RAS high time)
tPC	20 ns	25 ns	Page-mode read or write cycle time (/CAS to /CAS)
tAA	25 ns	30 ns	Access time: Column address valid to valid data out (includes address setup time before /CAS low)
tCAC	13 ns	15 ns	Access time: /CAS low to valid data out
tCAS	8 ns	10 ns	/CAS low pulse width minimum

Thus, the generally quoted number is the /RAS access time. This is the time to read a random bit from a precharged DRAM array. The time to read additional bits from an open page is much less.

When such a RAM is accessed by clocked logic, the times are generally rounded up to the nearest clock cycle. For example, when accessed by a 100 MHz state machine (i.e. a 10 ns clock), the 50 ns DRAM can perform the first read in five clock cycles, and additional reads within the same page every two clock cycles. This was generally described as "5‐2‐2‐2" timing, as bursts of four reads within a page were common.

When describing synchronous memory, timing is described by clock cycle counts separated by hyphens. These numbers representt_CL‐t_RCD‐t_RP‐t_RAS in multiples of the DRAM clock cycle time. Note that this is half of the data transfer rate when double data rate signaling is used. JEDEC standard PC3200 timing is 3‐4‐4‐8^[4] with a 200 MHz clock, while premium-priced high performance PC3200 DDR DRAM DIMM might be operated at 2‐2‐2‐5 timing.^[5]

	PC-3200 (DDR-400)				PC2-6400 (DDR2-800)				PC3-12800 (DDR3-1600)				Description
	Typical		Fast		Typical		Fast		Typical		Fast
	cycles	time	cycles	time	cycles	time	cycles	time	cycles	time	cycles	time
tCL	3	15 ns	2	10 ns	5	12.5 ns	4	10 ns	9	11.25 ns	8	10 ns	/CAS low to valid data out (equivalent totCAC)
tRCD	4	20 ns	2	10 ns	5	12.5 ns	4	10 ns	9	11.25 ns	8	10 ns	/RAS low to /CAS low time
tRP	4	20 ns	2	10 ns	5	12.5 ns	4	10 ns	9	11.25 ns	8	10 ns	/RAS precharge time (minimum precharge to active time)
tRAS	8	40 ns	5	25 ns	16	40 ns	12	30 ns	27	33.75 ns	24	30 ns	Row active time (minimum active to precharge time)

It is worth noting that the improvement over 11 years is not that large. Minimum random access time has improved from t_RAC = 50 ns tot_RCD + t_CL = 22.5 ns, and even the premium 20 ns variety is only 2.5 times better. CAS latency has improved even less, from t_CAC = 13 ns to10 ns. However, the DDR3 memory does achieve 32 times higher bandwidth; due to internal pipelining and wide data paths, it can output two words every 1.25 ns (1600 Mword/s), while the EDO DRAM can output one word per t_PC = 20 ns (50 Mword/s).